Conventionally, in this type of data processor testing apparatus, access data set in a cache memory or the like is generally invalidated (BI) by access made through an external unit such as an I/O.
FIG. 15 is a block diagram showing a data processor testing apparatus according to an example based on the conventional technology. The testing apparatus for a data processor shown in FIG. 15 comprises a CPU 81, an intermediate buffer 84, a memory 85 for storing therein data, and an external input/output mechanism 86 which is an external unit. It is assumed that this data processor testing apparatus, which is not shown in the figure, has a memory for a program required for executing the BI test.
The CPU 81 has an instruction cache memory 82, an operand cache memory 83 and an instruction control section 87, and controls the BI test on the whole using the instruction control section 87. The instruction control section 87 comprises an access instruction executing section 87A for executing an access instruction and a comparison control section 87B for comparing an expected value to a result of executing the BI test. The access instruction executing section 87A comprises an initialization control section 871 for initializing for a BI test for testing access data, an instruction string to be tested 872 indicating a sequence of the BI test, and an external input/output initiating section 873 for initiating input/output of the external I/O mechanism 86.
Connected to both the instruction cache memory 82 and the operand cache memory 83 are the instruction string to be tested 872 and the intermediate buffer 84 respectively, and an instruction and an operand are set in the cache memories via the intermediate buffer 84 by execution of the instruction string to be tested 872 respectively. Connected to the external I/O mechanism 86 are the external I/O initiating section 873 and the memory 85, and data is transmitted to and received from the memory 85 according to initiation for input/output from the external I/O control section 86. The intermediate buffer 84 is connected to the memory 85 and stores therein any instruction and operand read out therefrom by memory control.
Next description is made for operations of the data processor testing apparatus. In the data processor testing apparatus shown in FIG. 15, at first, in the access instruction executing section 87A, initialization is executed by the initialization control section 871, and then the instruction string to be tested 872 is executed. With the execution of this instruction string to be tested 872, the instruction and operand stored in the memory 85 are stored in the instruction cache memory 82 and operand cache memory 83 respectively via the intermediate buffer 84.
Further, when the external I/O mechanism 86 is initiated by the external I/O initiating section 873, the memory 85 is accessed by the external I/O mechanism 86. In this case, when an address of access from the external I/O mechanism 86 and an address of access by the instruction string to be tested 872 are in the same memory area, BI signals are issued, as shown in FIG. 15, from the memory 85 to the instruction cache memory 82, operand cache memory 83, and to the intermediate buffer 84 in order to match the access data (instruction data, operand data). The access data is invalidated by means of the BI signals in the instruction cache memory 82, operand cache memory 83, and intermediate buffer 84.
Then determination is made in the instruction control section 87 as to whether a result of the BI test is acceptable or not by comparing a result of execution of the instruction string to be tested 872 to a preset expected value in the comparison control section 87B. Then, the control shifts to the access instruction executing section 87A and the BI test is repeatedly executed.
In the conventional type of BI test, correlation among the instruction cache memory, operand cache memory and intermediate buffer is not clearly understood unless the external unit is connected to the apparatus for each verification form (logic verification, board verification, and actual machine verification), so that it is naturally required to construct a large verification system. However, because of restriction in the scale of logic simulation, there are some cases where verification can not be executed for some reasons such that all the circuits required for the verification system can not be embedded in an board or an external unit can not logically be connected to the apparatus. And for this reason, there occurs the necessity of executing again the entire test right from the beginning, which causes the work efficiency to get worse.